`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/05 23:44:36
// Design Name: 
// Module Name: axi_master
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module axi_master(
input logic ACLK,
input logic ARESETn,
//
output logic ARVALID,
output logic [31:0] ARADDR,
output logic [7:0] ARLEN,
input logic ARREADY,
//
input logic [31:0] RDATA,
input logic RVALID,
input logic RLAST,
input logic [1:0] RRESP,
output logic RREADY
    );
//
task send_req;
   input [31:0] rd_len;
   input [31:0] rd_addr;
   //
   ARVALID=0;
   ARADDR=rd_addr;
   ARLEN=rd_len;
   @(posedge ACLK);
   ARVALID=1;
   wait(ARREADY==1'b1);
   @(posedge ACLK);
   ARVALID=0;
endtask
//
initial
begin
    send_req(7,0);
	send_req(7,32);
	send_req(7,64);
	send_req(7,96);
	//
	send_req(7,8);
	send_req(7,16);
	send_req(7,24);
	send_req(7,40);
	send_req(7,48);
	send_req(15,72);
end
//RREADY
always_ff@(posedge ACLK,negedge ARESETn)
if(~ARESETn)
    RREADY<=0;
else 
    RREADY<=1;
//
endmodule
